Storage device including multi data rate memory device and memory controller

ABSTRACT

A memory controller is used to control a first storage block having a first data rate and a second storage block having a second data rate. The memory controller includes; a memory interface that transceives a data signal and a data strobe signal with the first and second storage blocks, and a sub controller that stores access information about the first data rate and the second data rate. The sub controller may include a delay lookup table storing access information including first strobe adjustment timing information defining a first data strobe signal provided to the first storage block, and second strobe adjustment timing information defining a second data strobe signal provided to the second storage block.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No.10-2017-0148321 filed on Nov. 8, 2017, the subject matter of which ishereby incorporated by reference.

BACKGROUND

The inventive concept relates to a storage device including a multi datarate memory device and a memory controller for same. More particularly,the inventive concept relates to a memory controller for a storagedevice including a sub controller that controls operations directed tostorage blocks having different data rates.

In order to control memories or storage devices having differentoperating speeds a number of corresponding channels are usuallyrequired. The memory controller may include channel interfacescorresponding to the respective channels, where each channel interfacemay modulate a reference clock signal and transceive signals viaconnected channels in synchronization with the modulated reference clocksignal.

A delay locked loop (DLL) circuit may be used to control a delay line,such that the phase of an input reference clock signal matches phase(s)of feedback signals output through the delay line. A master DLL circuitmay detect a lock value corresponding to a lock state and provide thelock value to a slave DLL circuit.

SUMMARY

The inventive concept provides a memory controller capable ofcontrolling a plurality of memories or storage devices having reducedchip sizes and different operating speeds, and a storage deviceincluding the memory controller.

In one embodiments the inventive concept provides a memory controllerconfigured to control a first storage block operating at a first datarate and a second storage block operating at a second data ratedifferent from the first data rate. The memory controller includes; amemory interface configured to transceive data signal and a data strobesignal with the first storage block and the second storage block, and asub controller including a delay lookup table storing access informationincluding first strobe adjustment timing information defining a firstdata strobe signal provided to the first storage block, and secondstrobe adjustment timing information defining a second data strobesignal provided to the second storage block.

In another embodiment, the inventive concept provides a storage deviceincluding; a first storage block having a first operating speed, asecond storage block having second operating speed different from thefirst operating speed, a memory controller configured to controloperation of the first storage block and the second storage block, and achannel configured to connect the memory controller with the firststorage block, and the second storage block. The memory controllerincludes; a memory interface configured to transceive a data signal anda data strobe signal with the first storage block and the second storageblock via the channel, and a sub controller configured to store accessinformation about the first operating speed and the second operatingspeed, wherein the access information is sequentially provided to thememory interface by the sub controller.

In another embodiment, the inventive concept provides a storage blockincluding; a first storage block having a first operating speed and asecond storage block having a second operating speed different from thefirst operating speed, a memory controller configured to control anoperation of the first storage block and the second storage block, and achannel configured to connect the memory controller with the firststorage block and the second storage block. The memory controllerincludes; a sub controller configured to store access informationassociated with the first storage block and the second storage blockbased on respective operating priorities for the first storage block andthe second storage block, and a multi clock generator configured togenerate a plurality of clock signals having different frequencies.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the inventive concept will be more clearly understoodfrom the following detailed description taken in conjunction with theaccompanying drawings in which:

FIG. 1 is a block diagram illustrating an electronic system according toan embodiment of the inventive concept;

FIG. 2 is a block diagram further illustrating in one example the memorycontroller of FIG. 1 according to an embodiment of the inventiveconcept;

FIG. 3 is a block diagram further illustrating the storage device ofFIG. 1 according to an embodiment of the inventive concept;

FIG. 4 is a conceptual diagram illustrating a delay lookup table thatmay be included in the memory controller of FIG. 3;

FIGS. 5A and 5B are respective timing diagrams illustrating an approachof delaying various signals provided to the multi data rate memorydevice of FIGS. 1 and 3;

FIG. 6 is a conceptual diagram illustrating the use of a first in firstout (FIFO) with the memory controller of FIGS. 1 and 3;

FIG. 7 is a block diagram illustrating another storage device accordingto embodiments of the inventive concept;

FIGS. 8A and 8B are respective circuit diagrams illustrating possibleapproaches to the operation of the sub controller of FIG. 7; and

FIGS. 9 and 10 are respective block diagrams illustrating in variousembodiments the multi clock generator of FIG. 7.

DETAILED DESCRIPTION

Hereinafter, embodiments of the inventive concept will be described insome additional detail with reference to the accompanying drawings.

Figure (FIG. 1 is a block diagram illustrating an electronic system 1generally including a storage device 10 and a host 20. The storagedevice 10 may be a solid state drive (SSD). However, the inventiveconcept is not limited thereto, and the storage device 10 may beimplemented in a variety of forms, such as an embedded multimedia card(eMMC), a universal flash storage (UFS), a compact flash (CF) card, asecure digital (SD) card, a micro-SD card, a mini SD card, an extremedigital (xD) card, and a memory stick.

The storage device 10 and host 20 may communicate via one or moreinterfaces. For example, using a competent interface the host 20 maytransmit a command CMD and corresponding data to the storage device 10.In this regard the command CMD may be understood as defining a requestthat the storage device perform a particular data processing operation(e.g., a read operation, a write operation, an erase operation, a sometype of housekeeping operation, etc.).

The host 20 may variously implemented using software and/or hardwareresources. For example the host 20 may be a central processing unit(CPU), a generic processor, a microprocessor, an application processor(AP), or the like. In certain embodiments of the inventive concept, thehost 20 may be implemented as a System-on-Chip (SoC).

Examples of interfaces that may be used to facilitate communicationbetween the storage device 10 and host 20 include interfaces operatingaccording to one or more conventionally understood technicalspecifications, such as the advanced technology attachment (ATA), serialATA (SATA), external SATA (e-SATA), small computer small interface(SCSI), serial attached SCSI (SAS), peripheral component interconnection(PCI), PCI express (PCI-E), IEEE 1394, universal serial bus (USB), an SDcard interface, a multimedia card (MMC) interface, an embeddedmultimedia card (eMMC) interface, and CF card interface.

In the illustrated example of FIG. 1, the storage device 10 includes amulti data rate memory device 300 including storage blocks respectivelycapable of operating at different data rates. Here, each “storage block”may be physically implemented using one or more chips, but nonethelessmay be variously accessed by the memory controller 100 and/or host 20 asa defined storage block having a defined data rate (i.e., a rate atwhich data may be accessed during one or more operations). In thisregard, the data rate of a particular storage device may vary accordingto operating mode, power conditions, user settings, etc., but for anygiven moment in time the operation of the storage device may be defineda current data rate.

The multi data rate memory device 300 of FIG. 1 may be variouslyimplemented, for example, in flash memory or a resistive memory such asresistive read-only memory (RAM) (ReRAM), phase change RAM (PRAM), andmagnetic RAM (MRAM). In certain embodiments of the inventive concept,the multi data rate memory device 300 may implemented using anintegrated circuit (IC) including a processor and RAM, such as a storagedevice and a processing in memory (PIM).

In this regard, the flash memory included in the multi data rate memorydevice 300 may be implemented in configurations including one or morethree-dimensional (3D) memory array(s). A 3D memory array may bemonolithically formed on at least one physical level of memory arrayswhich include an active region on a silicon substrate and a circuitrelated with operation of the memory cells on or in the siliconsubstrate. Here, the term “monolithic” denotes that layers for eachlevel constituting the memory cell array are directly stacked above thelayers of each lower level of the memory cell array. In one embodimentof the inventive concept, the 3D memory array may include vertical NANDstrings arranged in a vertical direction, such that at least one memorycell is arranged above another memory cell, where the at least onememory cell includes a charge trapping layer.

The provision, configuration and operation of memory devices including3D memory array(s) may be further understood by a review of U.S. Pat.Nos. 7,679,133; 8,553,466; 8,654,587; and 8,559,235, as well aspublished U.S. Patent Application 2011/0233648, the collective subjectmatter of which is hereby incorporated by reference.

Returning to FIG. 1, the storage device 10 include a memory controller100 that may be variously configured and operated to control theperformance of various data processing operations by the multi data ratememory device 300. And although not shown in FIG. 1, the storage device10 may include a buffer memory (e.g., a volatile memory such as dynamicRAM (DRAM) or static RAM (SRAM)) to temporarily store data during theperformance of read/write operations.

The memory controller 100 of FIG. 1 is shown controlling the operationof the multi data rate memory device 300 using a single channel CHconnecting memory controller 100 with the multi data rate memory device300. This is, of course, a simplified example used for clarity ofdescription and a multiplicity of channels may be used to interoperatethe memory controlled 100 and multi data rate memory device 300.However, in the context of the example illustrate din FIG. 1, the memorycontroller 100 may sequentially control storage blocks included in themulti data rate memory device 300 via channel CH.

In certain embodiments of the inventive concept, one or more memories(e.g., a buffer memory or register) or other component associated with(e.g., internally provided, or externally access by) the memorycontroller 100 may be used to store “access information” using (e.g.,)lookup table(s) and/or scheduler(s), where the access information isrespectively associated with storage blocks. In this context, the lookuptable(s) and/or scheduler(s) may be variously configured to store theaccess information. Further, the access information may be variouslydefined (e.g., stored, formatted, error corrected, etc.) for storage andaccess (e.g., reference) by the memory controller 100. However providedor defined, the memory controller 100 may use the access information torespectively (e.g., sequentially) control the storage blocks included inthe multi data rate memory device 300. Examples of the memory controller100 will be described hereafter in some additional detail with referenceto FIGS. 2 and 3.

FIG. 2 is a block diagram further illustrating in one implementation thememory controller 100 of FIG. 1. The memory controller 100 may be acomponent provided in a storage device, such as an SSD or a memory card.

Referring to FIG. 2, the memory controller 100 include a sub controller110, a memory interface (I/F) 120, a host interface (I/F) 130, aprocessor 140, RAM 150, and a buffer 160. Although only one processor140 is shown in FIG. 2, the memory controller 100 may include more thanone processor.

In certain embodiments of the inventive concept, the sub controller 110may be used to store access information associated with a multi datarate memory device, such as the multi data rate memory device 300 ofFIG. 1.

In certain embodiments of the inventive concept, the sub controller 110may store access information characterizing an operating speed of eachof the storage blocks included in the multi data rate memory device 300.Additionally or alternatively, the access information may includeinformation used to adjust the timing of one or more strobe signal(s),such as a strobe signal used to properly synchronize a transceived datasignal with the internal operation (e.g., read/write operation) of aparticular storage block. Here, the term “transceived” is used to denotethe transmitting and/or receiving of a signal between two components).Additionally or alternatively, the access information may includescheduling or scheduling control information (e.g., schedule informationderived from a functioning scheduler). Scheduling information may beused, for example, to control the order (and/or timing) in which thememory controller 100 transceives a data signal (or more simply “data”)to and/or from (hereafter, “to/from”) each one of the storage blocks.

Referring to FIGS. 1 and 2, the memory controller 100 may communicatevarious signals with the host 20 via the host I/F 130, and with themulti data rate memory device 300 via the memory interface 120.

In certain embodiments of the inventive concept, the memory interface120 may be implemented as part of a memory physical layer, and as such,the memory interface 120 may include a master delay locked loop (DLL)circuit and a slave DLL circuit. The operation of the master DLL circuitand slave DLL circuit will be described hereafter in some additionaldetails with reference to FIG. 3.

Write data transceived from the host (HOST) 20 may be temporarily storedin the buffer 160 and then provided to the multi data rate memory device300. Read data transceived from the multi data rate memory device 300may be temporarily stored in the buffer 160 and then provided to thehost 20. Thus, the buffer 160 may regarded as a data cache and may bevariously implemented using ROM, PROM, EPROM, EEPROM, PRAM, flashmemory, SRAM, and/or DRAM.

The RAM 150 may be used as a working memory and may be variouslyimplemented, for example, with DRAM, SRAM, PRAM, and/or flash memory.

FIG. 3 is a block diagram further illustrating the storage device 10 ofFIG. 1 in some additional detail.

Referring to FIG. 3, the storage device 10 includes the memorycontroller 100, a channel 200, and the multi data rate memory device300. The memory controller 100 includes the sub controller 110 and thememory I/F 120 which provides a memory physical layer (PHY).

In FIG. 3, the multi data rate memory device 300 includes a firststorage block (storage block1) 300_1 and a second storage block (storageblock2) 300_2, where the first storage block 300_1 and the secondstorage block 300_2 operate at different data rates (i.e., differentdata access speeds for one or more operations). Although only twostorage blocks, are shown in FIG. 3, those skilled in the art willrecognize that the inventive concept is not limited thereto, and threeor more storage blocks may be connected to the memory controller 100 viaone or more channel(s) 200. In addition, the storage device 10 mayfurther include a plurality of storage blocks having different accessinformation and operating at different data rates. For example, thefirst storage block 300_1 may include a plurality of flash memories, andthe memory controller 100 may be connected to the plurality of flashmemories via the channel 200.

As previously noted, the sub controller 110 may serve as a source ofaccess information characterizing the storage blocks. Thus, in certainembodiments of the inventive concept, the sub controller 110 will store,retain, track, manage and/or update access information using variousdata structures and access techniques, such as those conventionallyassociated with lookup tables and schedulers. For example, the subcontroller 110 may provide a delay lookup table 111 and a scheduler 113.The delay lookup table 111 may be used to store access information(e.g., strobe adjustment timing information, or access information usedto adjust the timing of a data strobe signal) provided to and used bythe first and second storage blocks 300_1 and 300_2. The strobeadjustment timing information may describe start time, and end time, ora period adjustment for a data strobe signal used to synchronize a datasignal. In this regard, the delay lookup table 111 may store firststrobe adjustment timing information corresponding to the first storageblock 300_1 and second strobe adjustment timing information for thesecond storage block 300_2.

Recognizing that the first and second storage blocks 300_1 and 300_2included in the multi data rate memory device 300 operate at differentdata rates, and further recognizing that data will typically be writtento or read from a memory component on the rising and/or falling edge ofa data strobe signal, it is necessary to control the timing of a firstdata strobe signal (or a first application of a data strobe signal) forthe first storage block 300_1 and a second data strobe signal (or asecond application of the data strobe signal) for the second storageblock 300_2. Each storage block therefore requires its own “strobeadjustment timing information” to properly define this particularcontrol signal. One more detailed approach to the use of the delaylookup table 111 shown in FIG. 3 will be provided hereafter withreference to FIG. 4.

The scheduler 113 may be used to store additional access informationcharacterizing the data rate (or operating speed) of the first andsecond storage blocks 300_1 and 300_2 included in the multi data ratememory device 300. In one embodiment, the scheduler 113 may beimplemented with a first-in-first-out (FIFO), and in another embodiment,the scheduler 113 may be implemented with a linked list.

When the scheduler 113 is the FIFO, the scheduler 113 may sequentiallystore access information about the data rate (operating speed) of thefirst and second storage blocks 300_1 and 300_2 included in the multidata rate memory device 300. For example, access information about thedata rate the first storage block 300_1 may be stored in the scheduler113. such that the first storage block 300_1 transceives data with thememory controller 100 “ahead of” (temporally before) the second storageblock 300_2. Accordingly, the sub controller 110 may sequentiallyprovide a control signal CTRL to the memory physical layer 120 inaccordance with access information about data rate stored in thescheduler 113.

When the scheduler 113 is a linked list, access information about thedata rate of the first storage block 300_1 and the second storage block300_2 may be stored based on a priority of the operation for the firststorage block 300_1 and a priority of the operation for the secondstorage block 300_2. For example, unlike the FIFO approach describedabove, regardless of the order in which access information about therespective data rates of the first storage block 300_1 and secondstorage block 300_2 are stored, the access information about the datarate of the second storage block 300_2 may be output before or after theaccess information about the data rate the first storage block 300_1 isoutput, based on the priority.

Hence, a control signal CTRL may be defined by access informationrelated to respective strobe adjustment timing information stored in thedelay lookup table 111, and by independent access information about datarate controlling the memory physical layer 120. In combination orseparately, information about a first data rate for the first storageblock 300_1 and a second data for the second storage block 300_2 may besequentially output from the scheduler 113, and a first strobeadjustment timing for the first storage block 300_1 and a second strobeadjustment timing for the second storage block 300_2 may be sequentiallyoutput from the delay lookup table 111. In this manner, a first controlsignal CTRL1 corresponding to the first storage block 300_1 and a secondcontrol signal CTRL2 corresponding to the second storage block 300_2 maybe sequentially provided from the sub controller 110 to the physicallayer 120. A detailed description of an embodiment assuming the use of aFIFO scheduler 113 will be provided hereafter with reference to FIG. 6.

The memory physical layer 120 illustrated in FIG. 3 includes a masterDLL circuit 121 and a slave DLL circuit 123. The master DLL circuit 121receives a reference clock signal CLK from a clock signal generator (notshown) in the memory controller 100 and provides a number of delay cellscorresponding to the reference clock signal CLK as a lock value LCval.

In one embodiment, the reference clock signal CLK may be an operatingclock signal of the memory controller 100 or an operating clock signalof the first storage block 300_1. In this case, the operating clocksignal of the first storage block 300_1 may be faster than the operatingclock signal of the second storage block 300_2. In other words, theoperating speed (or data rate) of the first storage block 300_1 may befaster than the operating speed (or data rate) of the second storageblock 300_2.

In this regard, the master DLL circuit 121 and the slave DLL circuit 123may be variously implemented. For example, the master DLL circuit 121and/or the slave DLL circuit 123 may include a number of delay cells,each delay cell being implemented as a pair of inverters connected inparallel to modulate a frequency, and the number of delay cells beingconnected in series.

In the illustrated example of FIG. 3, the slave DLL circuit 123 receivesthe lock value LCval from the master DLL circuit 121, and may thensequentially provide (i.e., output) to the channel 200 a data strobesignal DQS having an operating frequency corresponding to the defineddata rate of the first storage block 300_1 and/or the second storageblock 300_2. This may be accomplished using a selected number of delaycells corresponding to the operating frequency of the reference clocksignal CLK. For example, when the lock value LCval corresponding to 200MHz is about 50 (i.e., when a number of delay cells used to generate a200 MHz reference clock signal CLK is 50), the slave DLL circuit 123 mayoutput the data strobe signal DQS having an operating frequency of 100MHz using 100 delay cells.

Having thus defined an appropriate operating frequency for the datastrobe signal DQS, the slave DLL circuit 123 may make adjustment to thisreference signal in accordance with strobe adjustment timing informationrespectively corresponding to the first storage block 300_1 and thesecond storage block 300_2, as provided (e.g.,) by the control signalCTRL received from the sub controller 110.

Conventionally, in order to transceive data with storage blocks such asa memory or a storage device having different operating speeds, channelscorresponding to respective storage blocks would be provided, and aplurality of slave DLL circuits or a plurality of master DLL circuitswould be connected to each storage block.

In contrast, the memory controller 100 and storage device 10 includingthe memory controller 100 according to embodiments of the inventiveconcept may include the sub controller 110 described above, such thatdata may be sequentially transceived with the first and second storageblocks 300_1 and 300_2, despite the fact that the different storageblocks operate ad different data rates. Using a single memory physicallayer 120, a single master DLL circuit 121, and a single slave DLLcircuit 123 to accomplish this outcome allows for notable reductions inoverall chip size for the memory controller 100. In addition, when a newstorage block is to be connected to the memory controller 100, since inmany contemporary architectures it is possible to selectively storageblocks to a channel 200, only information associated with the newstorage block need be stored (or updated to) the delay lookup table 111and/or the scheduler 113. It is not necessary to manufacture a newmemory controller.

FIG. 4 is a conceptual diagram illustrating one possible version of thedelay lookup table 111 included in the memory controller 100.

Referring to FIGS. 3 and 4, the delay lookup table 111 may be used tostore various strobe adjustment timing information for a data strobesignal used to control transceiving of data in relation to a pluralityof storage blocks included in the multi data rate memory device 300connected to the channel 200. For example, in one implementation,respective strobe adjustment timing information may take the form of adelay time. Each delay time may denote a time delay (+/−) from a starttime for the data strobe signal. Here, delay times may be expressed asportions of a reference clock period, and may be defined in relation toa falling signal edge and/or a rising signal edge. Thus, the delay timemay be a time duration, from an arbitrarily selected start time at whichthe edge of the data strobe signal is expected (e.g., one-quarter of theclock period for the reference clock signal). For example, the delaytime may a delay from a time point at which the data signal starts,after a one-quarter value of a clock period of the reference clocksignal has passed, to a time point at which an edge of the data strobesignal starts.

In the illustrated example of FIG. 4, the multi data rate memory deviceis assumed to include first, second, third and fourth storage blocks(storage block1, storage block3, storage block3 and storage block4).Respective first, second, third and fourth data strobe signals are usedto control the transceiving of data. Thus, with reference to a controlsignal (e.g., data strobe signal DQS) data is transceived with the firststorage block1 using a first data strobe signal characterized by a firstdelay time TDLY1; data is transceived with the second storage block2using a second data strobe signal characterized by a second delay timeTDLY2; data is transceived with the third storage block3 using a thirddata strobe signal characterized by a third delay time TDLY3; and datais transceived with the fourth storage block4 using a fourth data strobesignal characterized by a fourth delay time TDLY4. Only four delay timesare illustrated in FIG. 4, but the inventive concept is not limitedthereto. The number of delay times stored in the delay lookup table 111will vary with the number of storage blocks included in the multi datarate memory device.

Of further note, even when the first, second, third and fourth storageblocks are homogeneously implemented using the same type of memorydevice (e.g., flash memory), the respective storage blocks maynonetheless exhibit different operating speeds (data rates) whenconnected to and/or operated by the memory controller 100. Hence, eachstorage block of a multi data rate memory device will require respectivestorage adjustment timing information stored in the delay lookup table111.

Not surprisingly, embodiments of the inventive concept are particularlywell suited to heterogeneously implemented storage devices. That is,respective operating speeds for flash memory, various resistive memoriesand PIM including a field programmable date array (FPGA) will varyconsiderably, and corresponding strobe adjustment timing informationwill vary accordingly. However, this is only illustrative, and theoperating speeds of the storage blocks included in a multi data ratememory device are not limited to these expressly identified memorytypes.

With regard to the embodiment illustrated in FIG. 4, two or more delaytimes may be stored for one storage block (e.g., mode-specific delaytimes) and delay times for storage blocks or other memories notconnected to channel 200 may also be stored in the delay lookup table111.

FIGS. 5A and 5B are respective timing diagrams explaining a delay timeaccording to an embodiment of the inventive concept. The timing diagramof FIG. 5A shows a delay time for the first storage block storageblock1, and the timing diagram of FIG. 5B shows a delay time for thesecond storage block storage block2.

Referring to FIGS. 3, 4 and 5A, the clock signal generator internal tothe memory controller 100 generate a reference clock signal CLKcorresponding to a fastest operating speed (data rate) for a particularstorage block among a plurality of storage blocks connected via channel200.

Assuming that the first storage block—among the first, second, third andfourth storage blocks—has a first data rate (corresponding to a fastestoperating speed), the clock signal generator may generate the referenceclock signal CLK having a first clock frequency corresponding to thefirst data rate. Hence, a first data strobe signal DQS1 associated withthe first storage block may have a frequency equal to (or otherwisedefined by) the first clock frequency of the reference clock signal CLK.Under these assumptions, the first delay time TDLY1 stored in the delaylookup table 111 may have a value of ‘0’, and the slave DLL 123 mayoutput the first data strobe signal DQS1 having a delay of one-quarterof the clock period TPD of the reference clock signal CLK based on thetime point at which the data signal DQ1 is generated.

Referring again to FIGS. 3, 4 and 5B, the second storage block has aslower operating speed (data rate) than the first storage block. Thus,the frequency of a second data strobe signal DQS2 for the second storageblock will lower than the frequency of the reference clock signal CLK,as defined above. Accordingly, the second delay time TDLY2 will have apositive value, and the slave DLL circuit 123 will output the seconddata strobe signal DQS2 by adding the second delay TDLY2 to the quartervalue of the clock period TPD of the reference clock signal CLK, basedon the time point at which the data signal DQ2 is generated.

In this manner as one example, a memory controller and a storage deviceincluding a multi data rate memory device including a memory controlleraccording to an embodiment of the inventive concept may efficientlygenerate a plurality of data strobe signals using a plurality of delaytimes, respectively associated with each one of a plurality of storageblocks. And since the different data strobe signals are generated usingthe different delay times stored prior to data processing operations,the overall burden placed on the memory physical layer may be reduced.Further, it is not necessary to separately provide a master DLL circuitor a slave DLL circuit corresponding to each of the plurality of thestorage blocks.

FIG. 6 is a conceptual diagram illustrating a FIFO 113_1 included in thememory controller 100 according to certain embodiments of the inventiveconcept.

Referring to FIGS. 3 and 6, the scheduler 113 if FIG. 3 may beimplemented as the FIFO 113_1 shown in FIG. 6. Here, access informationabout the operating speed (data rate) of the storage blocks (e.g.,storage block1 through storage block4) included in the multi data ratememory device 300 may be sequentially stored consistent withconventionally understood FIFO operating methods. For example, accessinformation associated with the first through fourth storage blocks maybe sequentially stored in the FIFO 113_1, such that resulting data maythen be sequentially transceived with the memory controller 100. In thiscase, the order in which the access information is input to, and outputfrom the FIFO 113_1 may be consistent with respective operating speedsfor the storage blocks. In other words, the slowest operating speed,then the next less slowest operating speed, etc. to the fastestoperating speed may be sequentially loaded into the FIFO 113_1.

In one embodiment, the FIFO 113_1 may be implemented with a memory, orthe FIFO 113_1 may be implemented with a plurality of registers.

Referring to FIGS. 1, 2 and 6, the processor 140 may be used to controlthe input/output of access information associated with the first throughfourth storage blocks in/from the FIFO 113_1 in response to acorresponding host command CMD. Under these assumptions, whenrespective, subsequent commands associated with data processingoperations (e.g., read/write operations) for the first through fourthstorage blocks are received from the host, the processor 140 maysequentially store access information about the first through fourthstorage blocks in the FIFO 113_1, based on respective priorities of theoperations of the first through fourth storage blocks which are receivedalong with the commands CMD. Accordingly, as illustrated in FIG. 6, anoperation by the first storage block storage will have a highestpriority, and an operation by the fourth storage block will have thelowest priority.

For example, when access information about the first storage block isreceived, the processor 140 may store the access information about thefirst storage block at an address indicated by a write pointer of theFIFO 113_1. Then the address indicated by the write pointer may beincremented. In this manner, the order in which the memory controller100 transceives data with the plurality of storage blocks may becontrolled by the processor 140. Of course, the sequential approachdescribed in relation to FIG. 6 is only one example of a controlapproach to the identification the storage blocks. However, assuming theforegoing, the sub controller 110 may sequentially provide the controlsignal CTRL to the memory physical layer 120 based on the accessinformation stored in the FIFO 113_1.

From the foregoing, it will be clear to one skilled in the art thataccess information in a variety of forms and definitions may be used tocontrol a memory physical layer in relation to a plurality of storageblocks.

Thus, recognizing that a memory controller may transceive data with aplurality of storage blocks having different operating speeds accordingto an order defined by access information stored (e.g.,) in a FIFO, thedifferent operating speeds of different storage blocks may beaccommodated in a multi data rate memory device. Further, when a newstorage block is connected to the memory controller, since it ispossible to connect storage blocks to a channel, only access informationrelated to new storage block must be stored (or updated) in the memorycontroller (e.g., a delay lookup table or scheduler 113 associated witha sub controller).

Although FIG. 6 illustrates an embodiment wherein the scheduler 113 isimplemented as a FIFO 113_1, the scheduler 113 may alternately beimplemented as a linked list. When the scheduler 113 is implemented as alinked list, an output order for the first through fourth storage blocksmay be stored based on a priority order of operations associated withthe first through fourth storage blocks.

FIG. 7 is a block diagram illustrating a storage device 10 a accordingto an certain embodiments of the inventive concept. Like referencenumbers used in FIG. 3 are used to indicate like elements in FIG. 7.FIGS. 8A and 8B are respective circuit diagrams illustrating examples ofsub controller 110 a shown in FIG. 7.

Referring to FIG. 7, the storage device 10 a includes the memorycontroller 100 a, the channel 200, and the multi data rate memory device300. The memory controller 100 a includes a sub controller 110 a and amemory physical layer 120 a.

The sub controller 110 a may include a scheduler 113 a and the multiclock generator 115. The scheduler 113 a may store information about theoperating speeds of the memory controller 100 a and the plurality ofstorage blocks 300_1 and 300_2.

The scheduler 113 a may be a FIFO or a linked list, and accessinformation about the operating speed of the first storage block 300_1,as well as access information about the operating speed of secondstorage block 300_2 may be sequentially stored in the FIFO or linkedlist. Accordingly, the sub controller 110 a may sequentially provide acontrol signal CTRL to the memory physical layer 120 a based on an orderdefined by access information stored in the scheduler 113 a.

The multi clock generator 115 may be used to generate multiple clocksignals having different frequencies. The clock signals generated by themulti clock generator 115 may include a first clock signal and a secondclock signal having frequencies corresponding to the operating speeds ofthe first storage block 300_1 and the second storage block 300_2,respectively. Possible configurations for the multi clock generator 115will be described hereafter with reference to FIGS. 9 and 10.

The control signal CTRLa may include information to control the memoryphysical layer 120 a. For example, the control signal CTRLa may includeaccess information defining the operating speed of the first storageblock 300_1 and the second storage block 300_2, and well as informationcharacterizing the clock signals generated by the multi clock generator115.

Referring to FIGS. 8A and 8B, in one embodiment, the sub controller 110a may include a selector 117 (e.g., a multiplexer (MUX)), and theselector 117 may be used to select and output respective clock signal(s)corresponding to access information about the operating speed(s) of thestorage blocks 300, as generated by the scheduler 113 a among the clocksignals having different frequencies generated by the multi clockgenerator 115.

For example, as illustrated in FIG. 8A, when access information aboutthe operating speed of the first storage block 300_1 (DATA RATE1) isoutput from the scheduler 113 a, the selector 117 may select and outputa first clock signal CLK1 having a frequency corresponding to theoperating speed of the first storage block 300_1 among the plurality ofclock signals generated by the multi clock generator 115. That is, thecontrol signal CTRLa may include the access information about theoperating speed of the first storage block 300_1 (DATA RATE1) and thefirst clock signal CLK1.

In contrast, as illustrated in FIG. 8B, when access information aboutthe operating speed of the second storage block 300_2 (DATA RATE2) isoutput from the scheduler 113 a, the selector 117 may select and outputa second clock signal CLK2 having a frequency corresponding to theoperating speed of the second storage block 300_2 among the plurality ofclock signals generated by the multi clock generator 115. That is, thecontrol signal CTRLa may include the information about the operatingspeed of the second storage block 300_2 (DATA RATE1) and the first clocksignal CLK2.

The configuration and operation of the sub controller 110 a are notlimited to those illustrated in FIGS. 8A and 8B, and the sub controller110 a need not necessarily include the selector 117. In anotherembodiment, the control signal CTRLa may include the plurality of clocksignals generated by the multi clock generator 115, and may betransmitted to the memory physical layer 120 a including the selector117. The selector 117 included in the memory physical layer 120 a maysequentially select and output the clock signal corresponding toinformation about the operating speeds of the plurality of storageblocks 300_1 and 300_2 sequentially output from the scheduler 113 a.

Referring again to FIG. 7, the memory physical layer 120 a may include amaster DLL circuit 121 a and a slave DLL circuit 123 a. Compared withthe memory physical layer 120 in FIG. 3, the memory physical layer 120 amay receive clock signals of various frequencies from the sub controller110 a while the memory physical layer 120 receives identical clocksignals.

The master DLL circuit 121 a may sequentially output a number of delaycells corresponding to sequentially received clock signals (e.g., thefirst clock signal CLK1 and the second clock signal CKL2) as a firstlock value and second lock value LCval_a1 and LCval_a2, respectively.The first lock value LCval_a1 may denote the number of delay cells thatdetect phase difference between the first clock signal CLK1 and a clockdelayed by the first clock signal CLK1 and make the phase differenceabout 0. The second lock value LCval_a2 may denote the number of delaycells that detect phase difference between the second clock signal CLK2and a clock delayed by the second clock signal CLK2 and make the phasedifference about 0. Since the frequencies of the first clock signal CLK1and the second clock signal CKL2 are different from each other, thefixed values LCval_a1 and LCval_a2 may also be different from eachother.

The slave DLL circuit 123 may sequentially receive the first lock valueLCval_a1 and the second lock value LCval_a2, and sequentially output tothe channel 200 a first data strobe signal and the second data strobesignal with operation frequencies corresponding to the first storageblock 300_1 and the second storage block 300_2, respectively.

The memory controller 100 a and the storage device 10 a including thememory controller 100 a according to an embodiment may include the subcontroller 110 a such that the memory controller 100 a sequentiallytransceives data with the storage blocks 300_1 and 300_2 havingdifferent operating speeds using one memory physical layer 120 a (e.g.,by using a single master DLL circuit 121 and a single slave DLL circuit123). In addition, since the plurality of storage blocks 300_1 and 300_2are connected to one channel 200, when a new storage block is to beconnected to the memory controller 100 a, it may not be necessary toconfigure a new channel and a new memory physical layer, which makes itadvantageous to manufacture a memory controller.

FIG. 9 is a block diagram further illustrating in one embodiment themulti clock generator 115 of FIG. 7.

Referring to FIGS. 7 and 9, the multi clock generator 115 includes aclock generator 115_1 and a plurality of clock modulators 115_2 and115_3. The clock generator 115_1 may be used to generate a master clocksignal MCLK.

The number of the plurality of clock modulators 115_2 and 115_3 may bedetermined based on the number of the plurality of storage blocks 300_1and 300_2 connected to the memory controller 100 a via the channel 200.In one embodiment, the multi clock generator 115 may include clockmodulators 115_2 and 115_3 as many as the number of storage blockshaving different operating speeds from each other.

Accordingly, the embodiment is not limited to including two clockmodulators 115_2 and 115_3 as illustrated in FIG. 8, but may alsoinclude three or more clock modulators.

In one embodiment, the first clock modulator 115_2 may receive themaster clock signal MCLK and modulate the master clock signal MCLK to afirst slave clock signal CLKs1. The first slave clock signal CLKs1 mayrefer to the first clock signal CLK1 in FIG. 7, and the first slaveclock signal CLKs1 may correspond to the operating speed of the firststorage block 300_1. The first slave clock signal CLKs1 may be used togenerate the first data strobe signal to transceive data with the firststorage block 300_1.

The second clock modulator 115_3 may receive the master clock signalMCLK and modulate the master clock signal MCLK into a second slave clocksignal CLKs2. The second slave clock signal CLKs2 may refer to thesecond clock signal CLK2 in FIG. 7 and the second slave clock signalCLKs2 may correspond to the operating speed of the second storage block300_2. The second slave clock signal CLKs2 may be used to generate thesecond data strobe signal to transceive data with the second storageblock 300_2. The first clock modulator 115_2 and the second clockmodulator 115_3 may generate the first slave clock signal CLKs1 and thesecond slave clock signal CLKs2 by modulating the frequency of themaster clock MCLK, respectively.

In another embodiment, the first slave clock signal CLKs1 and the masterclock signal MCLK may have the same frequency without a frequencymodulation operation performed by the first clock modulator 115_2 of themulti clock generator 115. Thus, the master clock signal MCLK may beused to generate the data strobe signal to transceive data with thefirst storage block 300_1. In other words, the clock generator 115_1 maygenerate the master clock signal MCLK based on the operating speed ofthe first storage block 300_1. For example, the clock generator 115_1may generate the master clock signal MCLK based on the operating speedof the storage block operating at a higher speed among the plurality ofstorage blocks 300_1 and 300_2.

FIG. 10 is a block diagram further illustrating an embodiment of themulti clock generator 115 of FIG. 7. In FIGS. 9 and 10, like referencenumbers denote like elements

Referring to FIGS. 7 and 9, the multi clock generator 115 a may includethe clock generator 115_1 and the plurality of clock modulators 115_2and 115_3. The clock generator 115_1 may generate the master clocksignal MCLK.

In one embodiment, the first clock modulator 115_2 may receive themaster clock signal MCLK and modulate the master clock signal MCLK to afirst slave clock signal CLKs1. The first slave clock signal CLKs1 maycorrespond to the operating speed of the first storage block 300_1. Thefirst slave clock signal CLKs1 may be used to generate the first datastrobe signal to transceive data with the first storage block 300_1.

The second clock modulator 115_3 may receive the first slave clocksignal CLKs1 from the first clock modulator 115_2 and may modulate thefirst slave clock signal CLKs2 to the second slave clock signal CLKs2.The second slave clock signal CLKs2 may correspond to the operatingspeed of the second storage block 300_2. The second slave clock signalCLKs2 may be used to generate the second data strobe signal totransceive data with the second storage block 300_2. The first clockmodulator 115_2 may modulate the frequency of the master clock MCLK togenerate the first slave clock signal CLKs1 and the second clockmodulator 115_3 may modulate the frequency of the first slave clocksignal CLKs1 to generate the second slave clock signal CLKs2.

In another embodiment, the multi clock generator 115 a may furtherinclude a third clock modulator, and the third clock modulator mayreceive the second slave clock signal CLKs2 from the second clockmodulator 115_3, modulate the frequency of the slave clock signal CLKs2to generate a third slave clock signal. That is, the multi clockgenerator 115 a need not separately include the first clock modulator115_2, and may use the master clock signal MCLK to generate the datastrobe signal for exchanging data with the first storage block 300_1. Inother words, the clock generator 115_1 may generate the master clocksignal MCLK based on the operating speed of the first storage block300_1.

While the inventive concept has been particularly shown and describedwith reference to example embodiments thereof, it will be understood byone of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the inventive concept as defined by the following claims.Accordingly, the true scope of protection of the inventive conceptshould be determined by the technical idea of the following claims.

What is claimed is:
 1. A memory controller configured to control a firststorage block operating at a first data rate and a second storage blockoperating at a second data rate different from the first data rate, thememory controller comprising: a memory interface configured totransceive data signal and a data strobe signal with the first storageblock and the second storage block; and a sub controller including adelay lookup table storing access information including first strobeadjustment timing information defining a first data strobe signalprovided to the first storage block, and second strobe adjustment timinginformation defining a second data strobe signal provided to the secondstorage block.
 2. The memory controller of claim 1, wherein the firstdata strobe signal is provided to the first storage block and the seconddata strobe signal is provided to the second storage block in asequential order defined by the access information.
 3. The memorycontroller of claim 2, further comprising: a clock generator thatgenerates a reference clock signal, wherein the first strobe adjustmenttiming information is a first time delay applied to the reference clocksignal to define the first data strobe signal, and the second strobeadjustment timing information is a second time delay, different from thefirst time delay, applied to the reference clock signal to define thesecond data strobe signal.
 4. The memory controller of claim 3, whereina frequency of the reference clock signal is identical to a frequency ofthe first data strobe signal.
 5. The memory controller of claim 1,wherein the memory interface comprises a single master delay locked loop(DLL) circuit and a single slave DLL circuit.
 6. The memory controllerof claim 1, wherein the sub controller comprises a First In First Out(FIFO), and the memory controller is configured to sequentially controloperation of the first storage block and the second storage block inresponse to access information about the first operating speed andaccess information about the second operating speed stored in the FIFO.7. The memory controller of claim 1, wherein the first storage block isa storage device and the second storage block is a processing in memory(PIM).
 8. A storage device comprising: a first storage block having afirst operating speed; a second storage block having second operatingspeed different from the first operating speed; a memory controllerconfigured to control operation of the first storage block and thesecond storage block; and a channel configured to connect the memorycontroller with the first storage block, and the second storage block,wherein the memory controller comprises: a memory interface configuredto transceive a data signal and a data strobe signal with the firststorage block and the second storage block via the channel; and a subcontroller configured to store access information about the firstoperating speed and the second operating speed, wherein the accessinformation is sequentially provided to the memory interface by the subcontroller.
 9. The storage device of claim 8, wherein the sub controllercomprises a First In First Out (FIFO) that stores the accessinformation, and the memory controller is further configured tosequentially control operation of the first storage block and thenoperation of the second storage block based on a sequence in which theaccess information is stored in the FIFO.
 10. The storage device ofclaim 8, further comprising: a processor configured to control an inputof access information to, and an output of access information from thesub controller.
 11. The storage device of claim 10, wherein theprocessor is configured to receive from a first command defining a firstoperation directed to the first storage block, a second command defininga second operation directed to the second storage block, and the firstoperation has a higher operating priority than the second operation. 12.The storage device of claim 11, wherein the processor is configured tostore the access information in the sub controller based on theoperating priority of the first operation and the operating priority ofthe second operation.
 13. The storage device of claim 8, wherein thememory controller is configured to transceive a data signal and a datastrobe signal with the first storage block and the second storage blockvia the channel, and the sub controller further comprises a delay lookuptable configured to store a first delay time for the data strobe signalas applied to the first storage block and a second delay time for thedata strobe signal as applied to the second storage block.
 14. Thestorage device of claim 8, wherein the sub controller further comprises:a multi clock generator configured to generate a plurality of clocksignals having different frequencies.
 15. The storage device of claim 8,further comprising: a third storage block having the first operatingspeed.
 16. A storage device comprising: a first storage block having afirst operating speed and a second storage block having a secondoperating speed different from the first operating speed; a memorycontroller configured to control an operation of the first storage blockand the second storage block; and a channel configured to connect thememory controller with the first storage block and the second storageblock, wherein the memory controller comprises: a sub controllerconfigured to store access information associated with the first storageblock and the second storage block based on respective operatingpriorities for the first storage block and the second storage block, andcomprising a multi clock generator configured to generate a plurality ofclock signals having different frequencies.
 17. The storage device ofclaim 16, wherein an output sequence for the access information isdetermined according to the respective operating priorities for thefirst storage block and the second storage block.
 18. The storage deviceof claim 16, wherein the multi clock generator comprises a referenceclock generator and a plurality of clock modulators.
 19. The storagedevice of claim 16, wherein the sub controller further comprises: aselector configured to receive the plurality of clock signals and selectone clock signal from among the plurality of clock signals based on theaccess information output from the memory.
 20. The storage device ofclaim 19, wherein the memory controller further comprises a singlemaster delay locked loop (DLL) circuit and a single slave DLL circuit,and the master DLL circuit and the slave DLL circuit are configured toreceive the selected clock signal and generate a signal transceived toat least one of the first storage block and the second storage block andcorresponding to the selected clock signal.